1. Field of the Invention
The invention relates to a digital frequency divider having a divider input for electrical input pulses and a divider output for an electrical output signal and comprising an N-position counter having a counter input and at least one counter output, wherein the divider input is coupled to the counter input and the divider output is connected to the counter output, which frequency divider further comprises a signal polarity switch and a B-position auxiliary counter of which an auxiliary counter input is coupled to a counter output of the N-position counter and an auxiliary counter output commands the signal polarity switch of which a switch input is coupled to the divider input and a switch output is coupled to the counter input of the N-position counter.
2. Description of the Prior Art
Frequency dividers of this type are commonly used to obtain pulse sequences with a lower pulse repetition frequency from a pulse source with a relatively high pulse repetition frequency, comprising a n-bit counter with N possible positions for dividing the higher frequency by a rational non-integer factor of the general form
N-A/B in which A, B and N are positive integers and in which A And B have no common divisor.
A frequency divider of the type mentioned above is described in the U.S. Pat. No. 3,896,387, especially in the embodiment as described in relation to FIGS. 7 and 8 of that specification, which frequency divider divides by a factor 4-(1/2)=31/2 in that example. For this purpose, the frequency divider comprises a signal polarity switch and a 2-position auxiliary counter of which an auxiliary counter input is coupled to the counter output of the N-position counter and an auxiliary counter output commands the signal polarity switch of which a switch input is coupled to the divider input and a switch output is coupled to the counter input of the N-position counter.
For the B-position auxiliary counter clearly b bits are necessary with B.ltoreq.2.sup.b.
Every time the output of the auxiliary counter output signal changes its polarity, the signal polarity switch switches the polarity of the incoming pulses, introducing a 180.degree. phase-lead. This has the same effect as adding one counting pulse at the output of the signal polarity switch for every output pulse of the auxiliary counter.
Considering a time interval in which the signal polarity switch presents B.times.N pulses at the counter input of the N-position counter, then in this time interval this number will be divided by N so that B pulses will be generated at the counter output of the N-position counter, enabling the B-position counter to count through a full B-position cycle. During such a cycle the auxiliary counter output generates an integer number of A.sub.1 pulses with A.sub.1 .ltoreq.B, depending on the way counter positions are decoded. Therefore, in the time interval considered, a number A.sub.1 of pulses generated by the auxiliary counter commanding the signal polarity switch has effected A.sub.1 extra pulses at the output of the signal polarity switch.
If the original number of pulses at the divider input during the time interval considered is denoted as P.sub.o, then clearly EQU B.times.N=P.sub.o +A.sub.1
or
P.sub.o =B.times.N-A.sub.1
In the same time interval the divider output receives B pulses from the counter output of the N-position counter, so that the ratio between the incoming and outgoing pulse frequencies is ##EQU1##
The embodiment in which the auxiliary counter is a divide-by-2 circuit is especially adapted for division by a factor N-1/2 as needed for video timing circuits for NTSC-video systems, as used in video games, Viewdata decoders or other digitized displays.
Although any rational non-integer divisor can be implemented with the embodiment as described above, this may lead to a costly implementation in some cases. For example: in the PAL-video system a colour subcarrier of 4433618.75 Hz nominal and a video line frequency of 15625 Hz nominal are required.
The first frequency can be derived from a standard PAL crystal oscillator for a frequency of twice the subcarrier frequency f.sub.sc using a divide-by-2 circuit. The second frequency would require a division by ##EQU2## which can be written as ##EQU3##
This means that the auxiliary counter seems to need 11 bits for counting through B=1250 positions.